Integrated circuits which utilize low voltage power supplies to reduce power consumption may require internal voltage boosting circuits to improve performance. These internal voltage boosting circuits typically generate signals at potentials which exceed the voltage level (Vcc) of the power being supplied to the integrated circuit. For example, in high capacity integrated circuit memory devices, such as dynamic random access memory (DRAM) devices which utilize low voltage power supplies, it has typically been necessary to utilize word line driver circuits to internally generate boosted voltage signals at potentials in excess of Vcc. These boosted voltage signals are typically supplied to word lines of the memory device to improve the reliability of operations to write and read data to and from an array of memory cells in the device. Exemplary voltage boosting circuits are illustrated by U.S. Pat. No. 5,467,032 to Lee, entitled "Word Line Driver Circuit For A Semiconductor Memory Device", assigned to the present assignee, the disclosure of which is hereby incorporated herein by reference.
Referring now to FIG. 1, an electrical schematic of a conventional word line driver circuit is illustrated. FIG. 2 is a timing diagram which illustrates operation of the driver circuit of FIG. 1. In particular, a conventional word line driver circuit includes a row decoder 1 which receives a first address signal Ai and generates a decoded word line signal .phi.S at an output thereof which is connected to a main word line MWL. A word line drive decoder 2 is also provided. The word line drive decoder 2 receives and decodes a second address signal Aj and generates true and complementary word line boost signals .phi.Xi and .phi.Xi. As illustrated by FIG. 2, the word line boost signal .phi.Xi may be provided as a boosted voltage signal having a magnitude of Vpp which is greater than Vcc. A pull-up driver 3 is also provided to boost a word line signal on a subordinate "sub" word line SWL which is electrically coupled to the main word line MWL, as illustrated. This sub word line may be electrically coupled to a portion of a row of memory cells in a memory array. Each of these memory cells may include an access transistor Tr having a drain electrically connected to a respective bit line BI and a source electrically connected to an electrode of a respective storage capacitor C, as illustrated.
Operation of the word line driver circuit of FIG. 1 will now be described with respect to FIG. 2. In particular, during an inactive state, the word line drive decoder 2 generates a word line boost signal .phi.Xi at a logic 0 potential and generates a complementary word line boost signal .phi.Xi at a logic 1 potential. The generation of these signals causes NMOS transistor M3 to be turned off (thereby electrically disconnecting the main word line MWL from the sub word line SWL) and NMOS transistor M4 to be turned on to thereby pull the sub word line SWL down to a ground reference potential (GND). The main word line MWL can then be driven to a logic 1 potential (e.g., Vcc) by the row decoder 1. This will cause the first node N1 to be driven to Vcc and the second node N2 to be driven to Vcc-Vth1, where Vth1 is the threshold voltage of NMOS transistor M1.
Next, the word line boost signal .phi.Xi is driven to a boosted voltage V.sub..phi.Xi (V.sub..phi.Xi =Vpp). In particular, this boosted voltage level V.sub..phi.Xi should be greater than Vcc by at least Vth2, where Vth2 is the threshold voltage of NMOS transistor M2. This causes NMOS transistor M3 to turn on and the fourth node N4 to be driven to Vpp. This also causes NMOS transistor M4 to be turned off. When NMOS transistor M3 turns on, the potential of the first node N1 is passed to the third node N3 at the sub word line SWL. Thus, the sub word line SWL can be driven to a logic 1 potential by the main word line MWL (e.g., Vcc-Vth3) once the word line boost signal .phi.Xi has been generated. As will be understood by those skilled in the art, the receipt of a boosted voltage V.sub..phi.Xi at the fourth node N4 (drain of NMOS transistor M2) will also cause the second node N2 (i.e., the gate of NMOS transistor M2) to be boosted to a voltage having a magnitude equal to Vcc-Vth1+.alpha.V.sub..phi.Xi. This boosting effect is a result of a "self-boosting" phenomenon which is caused by the presence of gate-to-drain capacitance C.sub.gd in NMOS transistor M2. The magnitude of this self-boosting effect is proportional to .alpha., where .alpha. represents a self-boosting ratio. As will be understood by those skilled in the art, this self-boosting effect permits the word line boost signal .phi.Xi to initially pass through the inversion-layer channel formed in the body region of NMOS transistor M2 without any appreciable voltage drop. Thus, the full potential of the word line boost signal .phi.Xi can essentially be passed to the third node N3 at the sub word line SWL without initially incurring a voltage drop of Vth2.
However, as the potential of the sub word line SWL is increased in the delay time period T.sub.D, as illustrated by FIG. 2, the effective threshold voltage Vth2 of the pull-up NMOS transistor M2 increases in response to a body-bias effect. The body-bias effect is caused by an increase in the reverse bias across the P-N junction formed between the inversion-layer channel and the body region of the NMOS transistor M2. Accordingly, the current driving capability of the NMOS transistor M2 decreases as the potential of the sub word line SWL increases. This decrease in current drive capability typically causes the delay time period T.sub.D associated with the transfer of the boost signal .phi.Xi to the sub word line SWL to increase. Accordingly, the voltage boosting capability of the word line driver circuit of FIG. 1 may be degraded by the body-bias effect and the access time associated with reading and writing data to the memory cell may be increased. This degradation in voltage boosting capability may become more severe as the voltage level of the power supply is decreased without a concomitant decrease in the threshold voltage of transistors in the driver circuits.
Thus, notwithstanding attempts to design word line driver circuits which provide voltage boosting capability, there continues to be a need for improved word line driver and related circuits which can provide enhanced voltage boosting capability even when operated at lower power supply voltages.